Wednesday, July 27, 2011

The Creative Break.....

.... didn't yield any fruits.

I'm stuck at several ends at the moment, mostly hardware-related as

- How to interface a larger number of 5V BiDir-Port to a 3.3V FPGA (Cartridge Ports and such)

- How to build some kind of SDCard-to-SPI-Interface which would enable upgrading the FPGA-Core, simpler than using a byteblaster.
As soon as I have figured out all hardware issues, I could advance to next next step(s)

On the HDL-Side, I can say that the solution fairly usable yet :) CPU/VIC/CIA are doing mostly fine, for the SID we have the SwinSid...

If anyone of you out there have any knowledge to share and would like to participate with this project, please contact me at!

1 comment:

  1. Don't rule out using a 5V tolerant CPLD for the buffering! It can save a lot of real estate and end up cheaper! In some cases it's also possible to reduce the pin count on your FPGA!

    SPI SD is trivial and has been done many times. The sticking point is reading the bitstream from a FAT filesystem. Easiest done with an external micro.