Ultimax-Module-Support has been added, so finally I can load the first game I've ever owned: Radar Rat Race!
Basic Sprice-Support added: The VIC-II can now display all 8 sprites, but only unexpanded and in single-color mode, no collisions. It's still a little buggy at the moment, but for the radar of Radar Rat Race it's ok. I also need invest some more time into the BA / AEC-Signals for proper, cycle-exact emulation.
Sunday, February 27, 2011
Tuesday, February 22, 2011
Update Week 08
The first commercial games are working! After implementing VIC-Raster-IRQs, almost all games I've tried are loading up and starting - with the "little" drawback that there are still no sprites, and I can only load 8k-Cartridges at $8000 - $9fff.
As of now, Gridrunner (Hires-Text) and Galaxian (Multicolor-Bitmap) are working perfectly, so does Pipes (except parts of the title screen which are made out of sprites).
As of now, Gridrunner (Hires-Text) and Galaxian (Multicolor-Bitmap) are working perfectly, so does Pipes (except parts of the title screen which are made out of sprites).
Friday, February 11, 2011
It's alive!
The first working version of my current project "C64 on an FPGA"!
Running on an Altera Cyclone II FPGA Dev-Board.
It's still in a very early stage. The CPU is pretty final, the other chips (VIC, CIA & Co.) only do what they need to do to get a very basic system running (e.g. the VIC does badlines for proper charmode, but no sprites or IRQs). SID is not implemented at all for the moment.
Video-Out is limited to black and white, as I'm still waiting for the ordered Video-DAC. The PAL-Signal is generated directly from the FPGA, using a minimal R2R-Net. The VIC would already be able to output 16 colors.
Running on an Altera Cyclone II FPGA Dev-Board.
It's still in a very early stage. The CPU is pretty final, the other chips (VIC, CIA & Co.) only do what they need to do to get a very basic system running (e.g. the VIC does badlines for proper charmode, but no sprites or IRQs). SID is not implemented at all for the moment.
Video-Out is limited to black and white, as I'm still waiting for the ordered Video-DAC. The PAL-Signal is generated directly from the FPGA, using a minimal R2R-Net. The VIC would already be able to output 16 colors.
Tuesday, February 1, 2011
The Hardware
This C64 on an FPGA-Project runs on this Board:
Core of the Board is an Altera Cyclone-II EP2C8Q208 FPGA. Although it's 'only' a mid-range FPGA, it offers enough power and logic units to hold a whole C64 including all the ROMs and the Color-RAM. For the normal 64k Ram, there is a 512Mbit SRAM on the board.
The Board does not have a Video/Composite-Out, so right now I'm abusing the HSync- and VSync-Pins of the VGA to generate 4 Signal Levels (Sync, Black, Grey and White) using a simple technique with 2 resistors (Based on the PIC Composite Out on Rickard's electronic project page (http://www.rickard.gunee.com/projects/video/pic/howto.php)).
The Video is only greyscale now, using a 32Mhz-Pulse Signal to get 9 Luma-Levels. They are far from beeing accurate, but the quality on a 1084 is fairly good. I'm going to visit the manufacturer of the FPGA-Board in march, he has prepared an AD725-Expansion for the board. The VIC-II Entity does already forward a 4Bit-Color-Index-Signal as well as HSync and VSync to the VideoOut-Entity, so the implementation of the AD725 should be quite easy.
There is no input besides the PS/2-Keyboard yet, I cannot plug a 1541 or anything. A bus driver IC, needed for the proper 5v <-> 3.3v Level Shifting, is on the way. At the moment, I can only compile 8k- and Ultimax-Cartridge-Files into the FPGA's Blockram.
The speed is virtually identical to a PAL C64 - the Master-Clock of the Board is 50Mhz, which goes into a PLL with a ratio of 29/46, giving an output clock of 31.5217MHz. This clock is divided again by 4 to get the pixel-clock (7.880 MHz), or by 32 to get the system clock (985054 Hz). Compared to the precise MHz figures at CodeBase64 (985248 Hz), it's less than 200 Hz off - 0.02%!
Core of the Board is an Altera Cyclone-II EP2C8Q208 FPGA. Although it's 'only' a mid-range FPGA, it offers enough power and logic units to hold a whole C64 including all the ROMs and the Color-RAM. For the normal 64k Ram, there is a 512Mbit SRAM on the board.
The Board does not have a Video/Composite-Out, so right now I'm abusing the HSync- and VSync-Pins of the VGA to generate 4 Signal Levels (Sync, Black, Grey and White) using a simple technique with 2 resistors (Based on the PIC Composite Out on Rickard's electronic project page (http://www.rickard.gunee.com/projects/video/pic/howto.php)).
The Video is only greyscale now, using a 32Mhz-Pulse Signal to get 9 Luma-Levels. They are far from beeing accurate, but the quality on a 1084 is fairly good. I'm going to visit the manufacturer of the FPGA-Board in march, he has prepared an AD725-Expansion for the board. The VIC-II Entity does already forward a 4Bit-Color-Index-Signal as well as HSync and VSync to the VideoOut-Entity, so the implementation of the AD725 should be quite easy.
There is no input besides the PS/2-Keyboard yet, I cannot plug a 1541 or anything. A bus driver IC, needed for the proper 5v <-> 3.3v Level Shifting, is on the way. At the moment, I can only compile 8k- and Ultimax-Cartridge-Files into the FPGA's Blockram.
The speed is virtually identical to a PAL C64 - the Master-Clock of the Board is 50Mhz, which goes into a PLL with a ratio of 29/46, giving an output clock of 31.5217MHz. This clock is divided again by 4 to get the pixel-clock (7.880 MHz), or by 32 to get the system clock (985054 Hz). Compared to the precise MHz figures at CodeBase64 (985248 Hz), it's less than 200 Hz off - 0.02%!
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